Scenarios

How RF teams apply Skycore in daily design

From first block generation to coverage closure, Skycore addresses the workflow stages where manual RTL work consumes the most pre-tapeout time.

RF IC Teams

Create LNA, PA, mixer, and synthesizer blocks

Each RF block has distinct performance parameters, port conventions, and topology limits. Skycore encodes them directly, so generated RTL follows your specification rather than a generic template.

Low-Noise Amplifier, LNA

Generate cascode and folded-cascode LNA RTL with NF, IIP3, and gain targets set as Verilog parameters. Choose differential or single-ended ports. Tested for 5G NR bands n77, n78, and n41.

RF chip design workspace with spectrum analyzer and PCB prototyping tools

Power Amplifier, PA

Generate Class-A, class-AB, and Doherty PA topologies with P1dB, PAE, and gain targets. Supports CMOS 65 nm to 28 nm and GaAs process nodes. Power control bus width follows your spec.

RF power amplifier on finned heatsink bench with power meter and coax connectors

RF Mixers

Generate active and passive mixer RTL with conversion gain, NF, and IIP3 parameters. Express LO-IF isolation needs as assertions. Supports up-conversion and down-conversion topologies.

RF mixer test bench with dual signal generators, mixer board, and spectrum analyzer

Frequency Synthesis

Generate integer-N and fractional-N PLL RTL with separate VCO, divider, and charge pump blocks, or as one integrated module. Phase noise and lock time targets flow into testbench assertions.

PLL synthesizer evaluation board linked to a phase-noise analyzer showing a noise skirt
Testbench Creation

Generate UVM testbenches without boilerplate

Verification engineers can spend weeks building mostly structural UVM infrastructure for each block. Skycore generates it, leaving your team to focus on corner-case sequences and coverage planning.

Full UVM hierarchy in one pass

Generate sequence, driver, monitor, scoreboard, and coverage collector together from the RTL interface spec. UVM components need no manual wiring.

Build coverage from parameter space

Functional coverage bins come from the block's declared RF performance range. Corner limits and operating-point transitions are covered by default, not found after first simulation.

EDA compile scripts included

Output packages pair VCS, Xcelium, and Questa compile scripts with the testbench SystemVerilog. Add them to your regression environment without adapter work.

Formal Analysis

Generate SVA assertions for key RF signal paths

Simulation alone under-tests RF parameter boundaries. Skycore generates SVA properties for the signal paths most important to each block type.

Parameter limit assertions

Generate SVA checks for every declared RF performance extreme. Verify NF, IIP3, and gain limits at RTL before simulation starts.

SVA Properties

RF path integrity checks

Encode differential signal balance, LO leakage limits, and power control transitions as assertions that the formal tool can prove.

Formal Checks

Detect unreachable states

Formal analysis finds RTL parameter combinations unreachable under stated interface constraints, helping remove dead parameter space early.

State Coverage

Describe your next block, view the output

Request early access, describe your circuit block, and get RTL plus testbenches the same day.

Request Early Access View the Platform