About

Built by engineers from years in the RTL-to-silicon loop

Skycore began inside a mixed-signal IC design consultancy. Measuring the engineer hours spent rewriting recurring UVM scaffolding showed us what needed fixing.

The problem we knew firsthand

RF IC teams are specialists. Their engineers spend years mastering noise figure, intermodulation, and phase noise. Yet much of their time goes to writing Verilog parameter bindings and UVM infrastructure built on predictable patterns. That was our first target.

The RTL generation agent began as a private tool in 2024. Once three separate design teams at two different consultancies used it, we knew the issue was broad. RF IC teams of any size hit the same wall at the same tapeout stage: a testbench sprint no one scoped properly.

Skycore was incorporated in Copenhagen in 2023, with the product dedicated to RF IC design workflows. We do not build general-purpose AI coding tools, only for the domain where time savings can alter team operations.

2024 Internal deployment at a mixed-signal consultancy
60% Per-block UVM scaffolding time reduction, measured across early access teams
Copenhagen Copenhagen incorporation in 2023, engineering and business co-located
Team

The team behind Skycore

Small team with RF IC design and ML infrastructure depth.

Pere Llimós
Pere Llimós Muntal
CEO and Co-Founder

Worked for years as an RF IC design engineer on mixed-signal and wireless chipset problems, then moved to applied ML tooling. Led tapeouts across multiple process nodes in sub-6 GHz and mmWave bands. A 5G front-end cycle went 6 weeks over schedule after poorly scoped verification rework, making the testbench bottleneck personal.

Ingrid Sondergaard
Ingrid Sondergaard
CTO and Co-Founder

Works in ML infrastructure and domain-specific code generation. She joined when the project was an internal script, rebuilt its training pipeline and inference stack from scratch, and owns RTL generation engine architecture plus the verification agent coordination layer. She favors domain-constrained code generation over generic completion.

Arjun Mehta
Arjun Mehta
Lead Verification Engineer

RF verification specialist with years in UVM methodology and testbench architecture for analog and mixed-signal blocks. Took Skycore's UVM scaffold generation from proof-of-concept to production. Ensures generated testbenches are behaviorally correct and EDA-tool compatible by default, rather than corrected in a later manual review.

Location

Copenhagen is home

Skycore ApS
Bredgade 25, 1050 Copenhagen K, Denmark
[email protected]
+45 33 91 20 45

Request early access

Early access teams receive hands-on onboarding, a free request block, and preview pricing locked for twelve months after general availability.