Verification
Custom Verification Rules for RF Block Libraries
Shared RF IP libraries often outgrow generic assertions. Learn how Skycore turns team-specific constraint conventions into reusable verification rules.
Engineering Blog
RTL Generation and RF Verification
Articles covering RF IC design, automated verification workflows, and the engineering of Skycore.
Integration
Where Skycore Adds RTL Generation to an EDA Flow
Adding a tool during tape-out is risky. See where Skycore fits in Cadence or Synopsys flows, without changing signoff tools.
Process
The Cost of RTL Iteration Before First Silicon
For fabless RF teams, every loop from spec change to simulation output consumes engineer-days. We traced where that time goes and what a shorter cycle could mean within a typical 6-month tapeout plan.
Verification
Formal Checks for RF Digital Control Interfaces
Formal methods add value beyond RF block simulation at the digital control layer. See the SPI and I2C register-map assertions Skycore generates.
Modeling
Capturing the Envelope in PA Behavioral Models
PA behavioral RTL must represent gain compression and AM-PM distortion without full circuit simulation at every iteration. See how Skycore generates PA behavioral RTL from spec input and selects modeling parameters.
Co-Design
Co-Designing Analog and Digital RTL at the Interface Boundary
Mixed-signal verification gets hardest at the analog-digital boundary. Skycore generates digital RTL and testbenches that directly exercise this interface.
Verification
Defining Meaningful Simulation Coverage for RF ICs
Digital coverage metrics say little about RF IP verification. Learn which spec-based checks matter for LNAs, mixers, and synthesizer loops.
Language
Choosing Verilog or SystemVerilog for RF Behavioral Blocks
When modeling RF blocks behaviorally, Verilog versus SystemVerilog affects more than syntax. See where each option helps the verification team in practice.
RTL Generation
How an LNA Specification Becomes Synthesizable RTL
A noise figure budget, gain target, and return loss requirement do not become useful RTL by direct conversion. We map the decisions involved and show which repetitive tasks Skycore automates while leaving design choices visible.
Verification
Automating Testbenches While Keeping the Test Strategy in Your Hands
Automated testbench generation removes boilerplate, but can also yield passing tests that never challenge the design. Clear constraints determine which outcome you get.
Process
Three RF IC Verification Chokepoints That Consume Team Time
Early access with several RF teams exposed three recurring verification delays: testbench setup, corner sweep scripts, and failure triage. Each costs days and needs a different remedy.
AI
Natural-Language RTL Generation: Current Strengths and Limits
Large language models can write plausible Verilog, yet plausible code may not synthesize or verify correctly. Skycore explains where natural-language RTL generation works today and where engineers must still review the result.