Platform

RF engineers get RTL generation plus verification

An RF-focused AI copilot understands performance limits, topology conventions, and UVM patterns, so each new block starts with working context.

RTL Synthesis

Turn plain language into synthesizable Verilog

State the block, target metrics, and process node. Skycore produces RTL with ports, parameter bindings, and synthesis constraints.

Generate RTL for major RF topologies

Generates topology-aware RTL for LNA, PA, mixer, VCO, and synthesizer blocks. Modules include suitable ports, parameters, and synthesis attributes for the selected process node.

  • NF, IIP3, gain, and P1dB map into Verilog parameters
  • Targets TSMC 28 nm, 40 nm, 65 nm, plus GF 22 nm FDX
  • Differential or single-ended ports fit downstream tool expectations
Engineer
Design a 2.4 GHz PA block, 65 nm CMOS, differential, target gain 22 dB, P1dB above 10 dBm
Skycore
Generating class-AB PA topology for 2.4 GHz, differential, 65 nm CMOS...
Output
module pa_24ghz (
input wire rf_inp, rf_inn,
output wire rf_outp, rf_outn,
input wire [2:0] pwr_ctrl
);
parameter real GAIN_DB = 22.5;
parameter real P1DB_DBM = 10.8;
endmodule
Block Type
Power Amplifier
Process
65 nm CMOS
Topology
Class-AB, diff
Testbenches
4 generated
Verification

Every RTL output includes an automated testbench

UVM scaffolding, scoreboards, and coverage collection run with generation. No separate verification sprint is required.

Generate a UVM environment with the RTL

Generated sequences, drivers, monitors, and scoreboards follow the RTL interface. Run the testbench in Cadence, Synopsys, or Mentor without manual wiring. Coverage and assertion results accompany the code.

  • Functional coverage follows declared parameters and interface contracts
  • SVA checks critical RF paths, including boundary conditions
  • RTL arrives with its coverage report and pass/fail result
Verification Agent - pa_24ghz
PASS tb_gain_vs_input_sweep
PASS tb_p1db_compression_check
PASS tb_differential_balance
WARN tb_pwr_ctrl_boundary_edge
3 passed, 1 warning (boundary margin narrower than spec at pwr_ctrl = 3'b000). Coverage: 94%.
Color-coded nodes depict an automated verification flow and test results
Capabilities

Features address concrete tapeout pain points

This is not general-purpose AI. Each module handles a defined stage of RF IC design and verification.

RF RTL Engine

Produces Verilog for RF constraints, including differential topologies and NF parameter bindings, rather than generic digital templates.

Verilog / SystemVerilog

UVM Testbench Builder

Sequences, drivers, monitors, and scoreboards follow the RTL interface. Run testbenches in your EDA environment without manual wiring.

UVM Testbenches

Coverage Gap Tracker

RTL generation includes functional coverage models. Coverage gaps appear with constraint suggestions, not only uncovered bins.

Functional Coverage

SVA Assertion Layer

Attach SVA properties to critical paths and corner boundaries, then run formal checks before simulation.

SVA Properties

Parameter Sweep Tool

Adjust NF, IIP3, gain, or bandwidth targets to view RTL parameter changes before choosing a topology for architecture trade studies.

Architecture Exploration

EDA Flow Export

Export packages contain synthesis scripts, simulation compile scripts, and waivers for Cadence, Synopsys, and Mentor flows.

Multi-tool Export

Fit Skycore into your workflow

Request early access and name your first block. RTL and testbenches return the same day.

Request Early Access Read the Quickstart Guide