Documentation

Skycore docs

Guides, reference content, and examples for adding Skycore to an RF IC design and verification workflow.

Begin here

The quickstart guide takes you through a first RTL generation request in under fifteen minutes. The API reference documents request parameters, response schemas, and error codes.

Quickstart
Create your first RF block and verify it in under fifteen minutes.
API Reference
Request and response schemas, authentication, rate limits, and error codes.
Examples
Worked LNA, PA, mixer, and synthesizer examples using real parameter sets.
Changelog
Release notes for new block types, model revisions, and API updates.
Getting Started Quickstart Authentication Your first request Output structure
API Reference Overview POST /generate POST /verify GET /status Error codes
Block Types LNA Power Amplifier Mixer Frequency Synthesizer VCO
Verification UVM testbenches SVA assertions Coverage reports

Skycore Platform Summary

Skycore produces synthesizable Verilog RTL and UVM verification environments for RF IC blocks. Specify the block type, performance targets, and process node. Skycore provides a complete RTL file, UVM testbench scaffold, SVA assertion properties, and coverage report.

The platform focuses on design stages with highly repetitive manual RTL work: block instantiation, parameter binding, testbench infrastructure, and assertion writing. It does not substitute for the RF engineering team's circuit design judgment.

RTL generation process

Provide a JSON description of the circuit block to generate. It specifies the block type, LNA, PA, mixer, VCO, or frequency synthesizer, target process node, RF performance parameters to encode as Verilog parameters, and topology constraints such as differential versus single-ended or class-A versus class-AB.

Skycore provides a complete Verilog module file. It contains port declarations aligned with block type conventions, parameter declarations carrying the RF performance targets, and synthesis attributes for the selected process node.

Verification and testbench outputs

Each RTL generation request supplies a UVM testbench scaffold in the output package. The scaffold connects a sequence, driver, monitor, scoreboard, and coverage collector to the generated RTL interface. SystemVerilog source comes with compile scripts for Cadence Xcelium, Synopsys VCS, and Mentor Questa.

Generated SVA assertion properties are separate files in the output package. They address the declared RF parameter boundary conditions and critical signal paths for the selected block type.

Output package layout

  • rtl/: generated Verilog module with include files
  • tb/: UVM testbench in SystemVerilog
  • tb/compile/: Xcelium, VCS, and Questa build scripts
  • assertions/: SVA assertion file for formal and simulation
  • coverage/: base coverage model and functional coverage groups
  • report.json: machine-readable report of parameters, block type, and verification outcomes

Need help?

For questions outside this documentation, email [email protected] or use the contact form. Early access teams receive onboarding assistance from the engineering team and have a dedicated support channel.

Resources

More reference material

Quickstart Guide
Step-by-step walkthrough from account access to first RTL output. Covers a worked LNA example on TSMC 65 nm with UVM testbench generation.
API Reference
Documentation for /generate, /verify, and /status includes request schemas, response formats, error codes, and rate limit details.
Block Examples
Examples cover every RF block type. Each provides the input description, generated RTL parameter set, and sample testbench output.